Job Overview:
The Principal Digital Layout Design Engineer will take a Technical Leadership role on the PCS digital layout design team as part of a SERDES Product Team located at Cork, Ireland.
Job Responsibilities:
• Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 5nm FinFET CMOS)
• Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure while working in collaboration with digital circuit designers
• Optimize and maintain the central RTL2GDS implementation/signoff flow which will be used by the global PD team
• The candidate will have the opportunity to work on many varieties of challenging designs, e.g. low power and high-speed design. The responsibility includes participating in or leading next-generation PHY IP physical design, methodology, and flow development
• The Candidate will work on the PPA target evaluation and co-work with the design and constraint team to improve the design, constraint, and brainstorm how to raise the PPA bar of next-generation PHY IP 2
• The Candidate will work on the new process physical implementation flow development such as TSMCN3
• Co-work with other functional teams (Design/STA/Analog/Package/Verification) to optimize the high-speed PHY IP development flow and define IP signoff criteria
• Work on the PHY IP physical implementation guide used for our customers and internal global PD teams • Participate in technical leadership of the PCS team in the areas of layout design from block level to PHY top level integration and sign off • Work with global teams (US, west coast and east coast), which work in different timezones
Job Qualifications:
• Candidate’s background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development.
• BEng, MEng or PhD Qualified.
• Architecture and implementation of complete PHY gds with integration of PMA, PCS hierarchies and optimized clock and power distribution strategies
• Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understanding deep sub-micron technology issues.
• Desire strong scripting skills and flow/CAD support experience. Solid knowledge of LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM
• Successful track record of taping out complex 16nm/10nm/7nm/5nm/3nm SOC chips
• Automation and programming-minded, solid coding experience in Tcl/Perl/Python.
• Strong physical implementation flow debugging skills
• Desire understanding RTL
• Working with layout designers from groups all over the world to build high quality IP and test chips
• Working with circuit designers and project managers from groups all over the world to understand their technical and schedule needs
• Innovative, self-motivated, excellent problem-solving skills, design aptitude, good communication skills and ability to work cooperatively in a team environment
Additional Skills/Preferences:
• Cadence tool experience and design experience at >10Gbps and in <40nm technologies
• Collaborating with the Cadence R&D teams (Virtuoso, PVS developers) to help develop the layout editing and verification tools and flows