Senior Analog Design Engineer (SERDES)
Location: Cork, Dublin, Galway
Reports to: Group Director
Job Overview:
The Cadence Serdes PHY team based at our R&D center of excellence in Cork, is seeking ambitious engineers who wish to work on the leading edge of Wireline technology at the highest data rates (112Gbps+) and on the smallest technology nodes (e.g. 3nm ).
The PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).
The Senior Analog Design Engineer will take a senior role on the PMA design team as part of a SERDES Product Team.
Job Responsibilities:
• Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS)
• Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications
• Work closely with Physical Design Engineers to design IC circuit blocks and PMA sections
• Work with Technical Team Leads in the areas of circuit design and SERDES architectures
• Mentor Junior Design Engineers when the project need arises
• Work with global teams (US, west coast and east coast), which work in different time-zones
Job Qualifications:
• BEng, MEng, PhD Qualified or equivalent.
• Candidate’s background should include a minimum of 4 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design
• Should have a good understanding of jitter and signal equalization techniques
• Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• Position requires proficiency in using CAD tools for circuit simulation, layout and physical verification
Additional Skills/Preferences:
• Cadence tool experience and design experience at >10Gbps and in <40nm technologies
• Lab test experience as part of silicon evaluation is advantageous
